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UP Core carrier board (low speed I/O)

Compatible with UP Core/ UP Core Plus and providing low-speed signal

See datasheet for more specifications datasheet

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Basic info
Part number UPC-CRSTL-A20-0001
Availability/Type Active
Carrier board Specification
CPLD/FPGA Intel Altera Max 10 for HAT 40-pin setting
USB to RS-232 1
Internal I/O ports 1 x jumper to RS232/422/485; 1x power LED (bottom side)
Rear I/O 1x RS-232/422/485 ( DB9 connector) 1x 12-24V power-input (+/- 10%) 1x horizontal 30-pin wafer box header for HAT 40-pin IO (GPIO, UART, I2C, SPI, PWM, I2S) 1x horizontal 20-pin wafer box header for Altera Max 10 resvered pins
Power requirement DC 5V from UP Core
Operation temperature 32°F ~ 140°F (0°C ~ 60°C)
Operation Humidity 0% ~ 90% relative humidity, non-condensing
Storage temperature -40°F ~ 176°F (-40°C ~ 80°C)
Certification CE/FCC Class A
Compatibility UP Core
Dimension 2.22"x 2.59" ( 56.50 mm × 66 mm)
HS Code 8473308000
Country of Origin Taiwan

More Info

The carrier board is designed to be compatible with UP Core/ UP Core Plus and providing low speed signal such as serial ports and more

1 x header 30 pin wafer box header for HAT 40 pin IO (GPIO, UART, I2C, SPI, PWM, I2S)


List of Contents


  • block diagram UPC-CRSTL-A20-0001 Size91.4 KB Download
  • UP Core carrier board design guide Size2.8 MB Download
  • UP SDK for Windows 10 and Windows IoT Size104.6 KB Download


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